{"id":91570,"date":"2024-04-18T15:41:49","date_gmt":"2024-04-18T07:41:49","guid":{"rendered":"https:\/\/www.techphant.cn\/?p=91570"},"modified":"2024-04-18T15:41:53","modified_gmt":"2024-04-18T07:41:53","slug":"fssmxp","status":"publish","type":"post","link":"https:\/\/www.techphant.cn\/blog\/91570.html","title":{"rendered":"FPGA\u662f\u4ec0\u4e48\u82af\u7247"},"content":{"rendered":"\n

\u3000\u3000FPGA(Field-Programmable Gate Array)\uff0c\u5373\u73b0\u573a\u53ef\u7f16\u7a0b\u95e8\u9635\u5217\uff0c\u662f\u4e00\u79cd\u7535\u5b50\u8bbe\u5907\uff0c\u7528\u4e8e\u6267\u884c\u4efb\u4f55\u6570\u5b57\u903b\u8f91\u529f\u80fd\u6216\u6570\u5b57\u7535\u8def\u7684\u786c\u4ef6\u5b9e\u73b0\u3002<\/strong>\u5b83\u662f\u5728PAL\u3001GAL\u3001CPLD\u7b49\u53ef\u7f16\u7a0b\u5668\u4ef6\u7684\u57fa\u7840\u4e0a\u8fdb\u4e00\u6b65\u53d1\u5c55\u7684\u4ea7\u7269\uff0c\u5c5e\u4e8e\u4e13\u7528\u96c6\u6210\u7535\u8def\u4e2d\u7684\u4e00\u79cd\u534a\u5b9a\u5236\u7535\u8def\u3002FPGA\u7531\u5927\u91cf\u7684\u903b\u8f91\u95e8\u3001\u5b58\u50a8\u5355\u5143\u548c\u53ef\u7f16\u7a0b\u8fde\u63a5\u5668\u4ef6\u7ec4\u6210\uff0c\u5177\u6709\u7075\u6d3b\u6027\u548c\u53ef\u91cd\u6784\u6027\uff0c\u80fd\u591f\u6839\u636e\u6240\u9700\u7684\u5e94\u7528\u6216\u529f\u80fd\u8981\u6c42\u8fdb\u884c\u91cd\u65b0\u7f16\u7a0b\u3002\u8fd9\u79cd\u7279\u6027\u4f7f\u5f97FPGA\u5728\u901a\u4fe1\u3001\u4eba\u5de5\u667a\u80fd\u3001\u82af\u7247\u8bbe\u8ba1\u7b49\u9886\u57df\u6709\u5e7f\u6cdb\u7684\u5e94\u7528\uff0c\u5e76\u4e14\u53ef\u4ee5\u7075\u6d3b\u5b9e\u73b0\u4e0d\u540c\u7684\u529f\u80fd\u3002\u6b64\u5916\uff0cFPGA\u8fd8\u5177\u6709\u5e76\u884c\u8ba1\u7b97\u548c\u9ad8\u6027\u80fd\u6570\u5b57\u4fe1\u53f7\u5904\u7406\u7684\u7279\u70b9\u3002<\/p>\n\n\n\n

\u3000\u3000\u4e00\u3001 FPGA\u7684\u5386\u53f2\u53d1\u5c55\u548c\u5173\u952e\u6280\u672f\u7a81\u7834\u662f\u4ec0\u4e48?<\/h2>\n\n\n\n

\u3000\u3000FPGA(\u73b0\u573a\u53ef\u7f16\u7a0b\u95e8\u9635\u5217)\u7684\u5386\u53f2\u53d1\u5c55\u548c\u5173\u952e\u6280\u672f\u7a81\u7834\u53ef\u4ee5\u4ece\u5176\u53d1\u660e\u3001\u53d1\u5c55\u9636\u6bb5\u4ee5\u53ca\u6280\u672f\u8fdb\u6b65\u7b49\u65b9\u9762\u8fdb\u884c\u6982\u8ff0\u3002<\/p>\n\n\n\n

\u3000\u3000FPGA\u7684\u53d1\u660e\u53ef\u4ee5\u8ffd\u6eaf\u52301984\u5e74\uff0c\u7531Xilinx\u7684\u521b\u59cb\u4ebaRoss Freeman\u7b49\u4eba\u53d1\u660e\u4e86\u7b2c\u4e00\u4e2a\u73b0\u573a\u53ef\u7f16\u7a0b\u95e8\u9635\u5217(FPGA)\uff0c\u5c3d\u7ba1\u76f4\u52301988\u5e74Actel\u666e\u53ca\u8fd9\u4e2a\u672f\u8bed\u4e4b\u524d\uff0c\u5b83\u4eec\u5e76\u4e0d\u88ab\u79f0\u4e3aFPGA\u3002\u8fd9\u6807\u5fd7\u7740FPGA\u6280\u672f\u7684\u8bde\u751f\uff0c\u968f\u540e\u8fd9\u4e00\u6280\u672f\u7ecf\u5386\u4e86\u51e0\u4e2a\u91cd\u8981\u7684\u53d1\u5c55\u9636\u6bb5\u3002<\/p>\n\n\n\n

\u3000\u3000\u5728FPGA\u7684\u53d1\u5c55\u5386\u7a0b\u4e2d\uff0c\u53ef\u4ee5\u5206\u4e3a\u4e09\u4e2a\u4e3b\u8981\u9636\u6bb5\uff1aFPGA 1.0(\u4e0a\u4e16\u7eaa80\u5e74\u4ee3\u523090\u5e74\u4ee3\u4e2d\u671f)\uff0c\u8fd9\u4e00\u65f6\u671f\u4e3b\u8981\u662f\u80f6\u5408\u903b\u8f91\u5355\u5143\uff0c\u5df2\u6709\u591a\u79cd\u4e0d\u540c\u7ed3\u6784\u7684\u53ef\u7f16\u7a0b\u903b\u8f91(PLD)\u88ab\u5de5\u4e1a\u754c\u91c7\u7528;FPGA 2.0\u548cFPGA 3.0\u7b49\u540e\u7eed\u9636\u6bb5\uff0c\u8fd9\u4e9b\u9636\u6bb5\u7684\u5177\u4f53\u65f6\u95f4\u7ebf\u548c\u7279\u5f81\u5728\u6211\u641c\u7d22\u5230\u7684\u8d44\u6599\u4e2d\u6ca1\u6709\u8be6\u7ec6\u8bf4\u660e\uff0c\u4f46\u53ef\u4ee5\u63a8\u65ad\u968f\u7740\u6280\u672f\u7684\u8fdb\u6b65\uff0cFPGA\u7684\u529f\u80fd\u548c\u5e94\u7528\u8303\u56f4\u4e0d\u65ad\u6269\u5927\u3002<\/p>\n\n\n\n

\u3000\u3000\u5173\u952e\u6280\u672f\u7684\u7a81\u7834\u63a8\u52a8\u4e86FPGA\u6280\u672f\u7684\u53d1\u5c55\u3002\u4f8b\u5982\uff0c\u968f\u7740\u53ef\u7f16\u7a0b\u903b\u8f91\u5355\u5143\u7684\u589e\u52a0\u548c\u903b\u8f91\u8d44\u6e90\u7684\u4f18\u5316\uff0cFPGA\u82af\u7247\u7684\u903b\u8f91\u5bc6\u5ea6\u548c\u8ba1\u7b97\u80fd\u529b\u5f97\u5230\u4e86\u663e\u8457\u63d0\u5347\u3002\u6b64\u5916\uff0c\u7b2c\u4e00\u4e2a\u767e\u4e07\u95e8\u7ea7\u7684\u9ad8\u7aefFPGA\u7684\u63a8\u51fa\uff0c\u91c7\u75280.25\u03bcm\u5de5\u827a\uff0c\u6807\u5fd7\u7740FPGA\u67b6\u6784\u5411\u524d\u8fc8\u4e86\u4e00\u5927\u6b65\uff0c\u6210\u4e3aASIC\u5668\u4ef6\u7684\u53ef\u7f16\u7a0b\u66ff\u4ee3\u9009\u62e9\u65b9\u6848\u3002\u8fd9\u4e9b\u6280\u672f\u8fdb\u6b65\u4e0d\u4ec5\u63d0\u9ad8\u4e86FPGA\u7684\u6027\u80fd\uff0c\u4e5f\u6269\u5927\u4e86\u5176\u5728\u5404\u884c\u5404\u4e1a\u7684\u5e94\u7528\u8303\u56f4\u3002<\/p>\n\n\n\n

\u3000\u3000\u8fd1\u5e74\u6765\uff0c\u56fd\u4ea7FPGA\u6280\u672f\u4e5f\u53d6\u5f97\u4e86\u663e\u8457\u8fdb\u5c55\u3002\u4e2d\u5fae\u4ebf\u82af\u5168\u9762\u638c\u63e1\u4e86FinFET FPGA\u6838\u5fc3\u6280\u672f\uff0c\u4e3a\u7528\u6237\u63d0\u4f9b\u66f4\u5168\u9762\u7684\u56fd\u4ea7\u53ef\u7f16\u7a0b\u7cfb\u7edf\u89e3\u51b3\u65b9\u6848\uff0c\u8fd9\u6807\u5fd7\u7740\u56fd\u4ea7FPGA\u6280\u672f\u5728\u81ea\u4e3b\u53ef\u63a7\u9053\u8def\u4e0a\u8fc8\u5165\u65b0\u9ad8\u5ea6\u3002<\/p>\n\n\n\n

\u3000\u3000FPGA\u7684\u5386\u53f2\u53d1\u5c55\u7ecf\u5386\u4e86\u4ece\u6700\u521d\u7684\u53d1\u660e\u5230\u6280\u672f\u7684\u4e0d\u65ad\u8fdb\u6b65\u548c\u5b8c\u5584\uff0c\u5173\u952e\u6280\u672f\u7a81\u7834\u5305\u62ec\u903b\u8f91\u5355\u5143\u7684\u589e\u52a0\u3001\u903b\u8f91\u8d44\u6e90\u7684\u4f18\u5316\u4ee5\u53ca\u5148\u8fdb\u5de5\u827a\u7684\u5e94\u7528\uff0c\u8fd9\u4e9b\u90fd\u6781\u5927\u5730\u63a8\u52a8\u4e86FPGA\u6280\u672f\u7684\u53d1\u5c55\u548c\u5e94\u7528\u9886\u57df\u7684\u6269\u5c55\u3002\u540c\u65f6\uff0c\u56fd\u4ea7FPGA\u6280\u672f\u7684\u8fdb\u6b65\u4e5f\u4e3a\u5168\u7403FPGA\u4ea7\u4e1a\u7684\u53d1\u5c55\u8d21\u732e\u4e86\u529b\u91cf\u3002<\/p>\n\n\n\n

\u3000\u3000\u4e8c\u3001 FPGA\u5728\u4eba\u5de5\u667a\u80fd\u9886\u57df\u7684\u5177\u4f53\u5e94\u7528\u6848\u4f8b\u6709\u54ea\u4e9b?<\/h2>\n\n\n\n

\u3000\u3000FPGA\u5728\u4eba\u5de5\u667a\u80fd\u9886\u57df\u7684\u5177\u4f53\u5e94\u7528\u6848\u4f8b\u5305\u62ec\uff1a<\/p>\n\n\n\n

    \n
  • \u3000\u3000\u89c6\u969c\u4eba\u58eb\u4fbf\u643a\u5bfc\u822a\u7cfb\u7edf\uff1a\u901a\u8fc7\u4f7f\u7528FPGA\u642d\u5efa\u7684\u4eba\u5de5\u795e\u7ecf\u7f51\u7edc\uff0c\u5b9e\u73b0\u4e86\u57fa\u4e8e\u6df1\u5ea6\u5b66\u4e60\u7684\u89c6\u969c\u4eba\u58eb\u4fbf\u643a\u5bfc\u822a\u7cfb\u7edf\uff0c\u8be5\u7cfb\u7edf\u5728\u7b2c\u516b\u5c4a\u534e\u4e3a\u676f\u4e2d\u56fd\u5927\u5b66\u751f\u667a\u80fd\u8bbe\u8ba1\u7ade\u8d5b\u4e2d\u83b7\u5f97\u4e86\u4e8c\u7b49\u5956\u3002<\/li>\n\n\n\n
  • \u3000\u3000\u667a\u80fd\u5b89\u68c0\u3001\u5de5\u4e1aOCR\u667a\u80fd\u8bc6\u522b\u3001\u519c\u4ea7\u54c1\u667a\u80fd\u5206\u9009\u3001\u7269\u6d41\u667a\u80fd\u5206\u79bb\u7cfb\u7edf\uff1a\u590d\u65e6\u5fae\u7535\u57fa\u4e8eFPGA\u8bbe\u8ba1\u7684PSOC\u4ea7\u54c1\u5728\u8fd9\u4e9b\u9886\u57df\u5df2\u7ecf\u6709\u5e94\u7528\u6848\u4f8b\u3002<\/li>\n\n\n\n
  • \u3000\u3000\u8fb9\u7f18\u4eba\u5de5\u667a\u80fd\u5e94\u7528\uff1a\u5229\u7528FPGA\u52a0\u901f\u795e\u7ecf\u7f51\u7edc(NN)\u6570\u5b66\u8fd0\u7b97\uff0c\u7279\u522b\u6709\u6548\u4e8e\u6267\u884c\u57fa\u4e8e\u786c\u4ef6\u7684\u9ad8\u6027\u80fd\u8ba1\u7b97\u5bc6\u96c6\u578b\u5de5\u4f5c\uff0c\u540c\u65f6\u529f\u8017\u76f8\u5bf9\u8f83\u4f4e\u3002<\/li>\n\n\n\n
  • \u3000\u3000\u5229\u7528DNNDK\u4f5cAI DPU\u786c\u6838\u52a0\u901f\u7684\u5c0f\u8f66\u9879\u76ee\uff1a\u901a\u8fc7\u5728\u5c0f\u8f66\u4e0a\u5b89\u653eUltra96\u548c\u6444\u50cf\u5934\uff0c\u5728\u884c\u8fdb\u8fc7\u7a0b\u4e2d\u5bf9\u6444\u50cf\u5934\u6240\u6444\u5165\u7684\u76ee\u6807\u548c\u9053\u8def\u8fb9\u7f18\u8fdb\u884c\u8bc6\u522b\u3002<\/li>\n\n\n\n
  • \u3000\u3000\u52a0\u901fAI\u63a8\u7406\u7684\u5e94\u7528\u6848\u4f8b\uff1a\u8d5b\u7075\u601d\u4e0eMipsology\u8fbe\u6210\u5408\u4f5c\u534f\u8bae\uff0c\u63a8\u5e7f\u548c\u9500\u552e\u57fa\u4e8eFPGA\u7684\u6df1\u5ea6\u5b66\u4e60\u52a0\u901f\u5361\uff0c\u4ee5\u52a0\u901f\u66f4\u591aAI\u5e94\u7528\u7684\u843d\u5730\u3002<\/li>\n<\/ul>\n\n\n\n

    \u3000\u3000\u8fd9\u4e9b\u6848\u4f8b\u5c55\u793a\u4e86FPGA\u5728\u4eba\u5de5\u667a\u80fd\u9886\u57df\u7684\u5e7f\u6cdb\u5e94\u7528\uff0c\u5305\u62ec\u4f46\u4e0d\u9650\u4e8e\u667a\u80fd\u5bfc\u822a\u3001\u5b89\u5168\u68c0\u67e5\u3001\u56fe\u50cf\u8bc6\u522b\u3001\u8fb9\u7f18\u8ba1\u7b97\u4ee5\u53caAI\u63a8\u7406\u52a0\u901f\u7b49\u65b9\u9762\u3002FPGA\u7684\u4f18\u52bf\u5728\u4e8e\u5176\u5e76\u884c\u8ba1\u7b97\u3001\u53ef\u5b9a\u5236\u548c\u9ad8\u901f\u6570\u636e\u5904\u7406\u7684\u80fd\u529b\uff0c\u8fd9\u4f7f\u5f97\u5b83\u80fd\u591f\u52a0\u901fAI\u7b97\u6cd5\u548c\u6a21\u578b\u7684\u6267\u884c\uff0c\u63d0\u9ad8AI\u7cfb\u7edf\u7684\u6027\u80fd\u548c\u6548\u7387\u3002<\/p>\n\n\n\n

    \u3000\u3000\u4e09\u3001 \u5982\u4f55\u6bd4\u8f83FPGA\u4e0e\u4f20\u7edfASIC(\u4e13\u7528\u96c6\u6210\u7535\u8def)\u7684\u6027\u80fd\u548c\u6210\u672c\u6548\u76ca?<\/h2>\n\n\n\n

    \u3000\u3000\u5728\u6bd4\u8f83FPGA\u4e0e\u4f20\u7edfASIC(\u4e13\u7528\u96c6\u6210\u7535\u8def)\u7684\u6027\u80fd\u548c\u6210\u672c\u6548\u76ca\u65f6\uff0c\u6211\u4eec\u9700\u8981\u4ece\u591a\u4e2a\u89d2\u5ea6\u8fdb\u884c\u5206\u6790\u3002<\/p>\n\n\n\n

    \u3000\u3000\u4ece\u6027\u80fd\u89d2\u5ea6\u6765\u770b\uff0cASIC\u901a\u5e38\u6bd4FPGA\u5177\u6709\u66f4\u9ad8\u7684\u6027\u80fd\u3002\u8fd9\u662f\u56e0\u4e3aASIC\u662f\u4e13\u95e8\u4e3a\u7279\u5b9a\u5e94\u7528\u7a0b\u5e8f\u800c\u8bbe\u8ba1\u7684\uff0c\u5176\u7535\u8def\u7ed3\u6784\u53ef\u4ee5\u9488\u5bf9\u7279\u5b9a\u7684\u4efb\u52a1\u8fdb\u884c\u4f18\u5316\uff0c\u4ece\u800c\u5b9e\u73b0\u66f4\u9ad8\u7684\u6027\u80fd\u3002ASIC\u7684\u8bbe\u8ba1\u6d41\u7a0b\u6bd4FPGA\u590d\u6742\u5f97\u591a\uff0c\u8bbe\u8ba1\u5bc6\u96c6\u5ea6\u4e5f\u66f4\u9ad8\uff0c\u6d89\u53ca\u4e03\u4e2a\u9636\u6bb5\u624d\u80fd\u5b8c\u6210\u8bbe\u8ba1\uff0c\u800cFPGA\u7684\u8bbe\u8ba1\u6d41\u7a0b\u7b80\u5355\u4e14\u901f\u5ea6\u66f4\u5feb\u3002\u6b64\u5916\uff0cASIC\u5728\u5927\u89c4\u6a21\u751f\u4ea7\u4e2d\u5177\u6709\u6210\u672c\u6548\u76ca\uff0c\u56e0\u4e3a\u91cf\u4ea7\u540e\u5e73\u5747\u6210\u672c\u8fdc\u4f4e\u4e8eFPGA\u3002\u7136\u800c\uff0cFPGA\u7684\u4e0a\u5e02\u901f\u5ea6\u5feb\u4e8eASIC\uff0c\u4f46\u6027\u80fd\u8f83\u4f4e\u3002<\/p>\n\n\n\n

    \u3000\u3000\u4ece\u6210\u672c\u6548\u76ca\u7684\u89d2\u5ea6\u6765\u770b\uff0cFPGA\u65b9\u6848\u65e0\u9700\u7b49\u5f85\u4e00\u4e2a\u5b63\u5ea6\u5230\u4e00\u5e74\u4e0d\u7b49\u7684\u82af\u7247\u6d41\u7247\u5468\u671f\uff0c\u4e14\u5c11\u4e86\u56fa\u5b9a\u6210\u672c\uff0c\u4e0d\u7528\u627f\u62c5\u6d41\u7247\u5931\u8d25\u98ce\u9669\uff0c\u5728\u6210\u672c\u4e0a\u66f4\u5177\u4f18\u52bf\u3002\u76f8\u6bd4\u4e4b\u4e0b\uff0cASIC\u7684\u5f00\u53d1\u5468\u671f\u8f83\u957f\uff0c\u56e0\u4e3a\u9700\u8981\u8fdb\u884c\u5b9a\u5236\u8bbe\u8ba1\u548c\u5236\u7a0b\u5de5\u827a\uff0c\u800c\u4e14\u5236\u9020\u6210\u672c\u4e5f\u8f83\u9ad8\u3002ASIC\u7684\u4e00\u6b21\u6027\u6210\u672c(\u5149\u523b\u63a9\u6a21\u5236\u4f5c\u6210\u672c)\u8fdc\u9ad8\u4e8eFPGA\u3002<\/p>\n\n\n\n

    \u3000\u3000FPGA\u4e0eASIC\u5404\u6709\u4f18\u52a3\u3002\u5982\u679c\u9879\u76ee\u9700\u8981\u5feb\u901f\u4e0a\u5e02\u3001\u9ad8\u7075\u6d3b\u6027\u4ee5\u53ca\u8f83\u4f4e\u7684\u4e00\u6b21\u6027\u6210\u672c\uff0cFPGA\u53ef\u80fd\u662f\u66f4\u597d\u7684\u9009\u62e9\u3002\u76f8\u53cd\uff0c\u5982\u679c\u9879\u76ee\u5bf9\u6027\u80fd\u6709\u6781\u9ad8\u8981\u6c42\uff0c\u4e14\u80fd\u591f\u627f\u53d7\u8f83\u957f\u7684\u5f00\u53d1\u5468\u671f\u548c\u8f83\u9ad8\u7684\u5236\u9020\u6210\u672c\uff0c\u90a3\u4e48ASIC\u5c06\u662f\u66f4\u5408\u9002\u7684\u9009\u62e9\u3002\u56e0\u6b64\uff0c\u5728\u9009\u62e9FPGA\u8fd8\u662fASIC\u65f6\uff0c\u9700\u8981\u6839\u636e\u5177\u4f53\u7684\u5e94\u7528\u9700\u6c42\u3001\u9884\u7b97\u9650\u5236\u4ee5\u53ca\u65f6\u95f4\u7d27\u8feb\u6027\u7b49\u56e0\u7d20\u7efc\u5408\u8003\u8651\u3002<\/p>\n\n\n\n

    \u3000\u3000\u56db\u3001 FPGA\u7684\u6700\u65b0\u6280\u672f\u8fdb\u5c55\u548c\u672a\u6765\u53d1\u5c55\u8d8b\u52bf\u662f\u4ec0\u4e48?<\/h2>\n\n\n\n

    \u3000\u3000FPGA(\u73b0\u573a\u53ef\u7f16\u7a0b\u903b\u8f91\u95e8\u9635\u5217)\u7684\u6700\u65b0\u6280\u672f\u8fdb\u5c55\u548c\u672a\u6765\u53d1\u5c55\u8d8b\u52bf\u4e3b\u8981\u4f53\u73b0\u5728\u4ee5\u4e0b\u51e0\u4e2a\u65b9\u9762\uff1a<\/p>\n\n\n\n

      \n
    • \u3000\u3000\u795e\u7ecf\u7f51\u7edc\u52a0\u901f\uff1aFPGA\u5728\u795e\u7ecf\u7f51\u7edc\u52a0\u901f\u65b9\u9762\u53d6\u5f97\u4e86\u663e\u8457\u8fdb\u5c55\uff0c\u7279\u522b\u662f\u5728\u795e\u7ecf\u7f51\u7edc\u91cf\u5316\u65b9\u9762\u3002\u901a\u8fc7\u964d\u4f4e\u7cbe\u5ea6\u7684\u8ba1\u7b97\u6765\u52a0\u901f\u795e\u7ecf\u7f51\u7edc\uff0c\u5229\u7528FPGA\u7684\u4f4d\u7ea7\u53ef\u91cd\u6784\u6027\uff0c\u8fd9\u5728\u4f20\u7edfCPU\u548cGPU\u4e0a\u662f\u65e0\u6cd5\u5b9e\u73b0\u7684\u3002<\/li>\n\n\n\n
    • \u3000\u3000\u5d4c\u5165\u5f0f\u7cfb\u7edf(SOPC)\u6280\u672f\uff1a\u57fa\u4e8eFPGA\u7684\u5d4c\u5165\u5f0f\u7cfb\u7edf(System on Chip\uff0cSoC)\u6280\u672f\u8d8a\u6765\u8d8a\u5e7f\u6cdb\u5730\u88ab\u91c7\u7528\u3002\u8fd9\u79cd\u6280\u672f\u7684\u6838\u5fc3\u662f\u5728FPGA\u82af\u7247\u5185\u90e8\u6784\u5efa\u5904\u7406\u5668\uff0c\u5982Xilinx\u516c\u53f8\u63d0\u4f9b\u7684\u57fa\u4e8ePower PC\u7684\u6280\u672f\u3002<\/li>\n\n\n\n
    • \u3000\u3000\u9ad8\u6027\u80fd\u548c\u9ad8\u53ef\u9760\u6027\uff1a\u672a\u6765FPGA\u7684\u53d1\u5c55\u65b9\u5411\u5c06\u662f\u63d0\u9ad8\u8ba1\u7b97\u901f\u5ea6\u548c\u6570\u636e\u5904\u7406\u80fd\u529b\uff0c\u540c\u65f6\u4fdd\u8bc1\u7cfb\u7edf\u7684\u7a33\u5b9a\u6027\u548c\u53ef\u9760\u6027\u3002\u8fd9\u610f\u5473\u7740FPGA\u5c06\u4e0d\u65ad\u63d0\u9ad8\u5176\u96c6\u6210\u5ea6\u3002<\/li>\n\n\n\n
    • \u3000\u3000\u901a\u4fe1\u548c\u5927\u6570\u636e\u5e94\u7528\uff1aFPGA\u5728\u901a\u4fe1\u9886\u57df\u7684\u5e94\u7528\u5c06\u7ee7\u7eed\u6269\u5927\uff0c\u4ece4G\u8fc7\u6e21\u52305G\uff0c\u5e76\u53ef\u80fd\u5728\u5927\u6570\u636e\u5904\u7406\u65b9\u9762\u53d1\u6325\u4f5c\u7528\u3002FPGA\u4e0eCPU\u534f\u540c\u8fdb\u884c\u6570\u636e\u5904\u7406\u5df2\u7ecf\u5728\u591a\u5bb6\u5927\u516c\u53f8\u5f97\u5230\u5e94\u7528\u3002<\/li>\n\n\n\n
    • \u3000\u3000\u6280\u672f\u521b\u65b0\u548c\u5e02\u573a\u6f5c\u529b\uff1aFPGA\u6280\u672f\u4ee5\u5176\u53ef\u7f16\u7a0b\u6027\u3001\u9ad8\u6027\u80fd\u548c\u4f4e\u529f\u8017\u7b49\u7279\u70b9\uff0c\u5728\u591a\u4e2a\u9886\u57df\u5c55\u73b0\u51fa\u5f3a\u5927\u7684\u5e94\u7528\u6f5c\u529b\uff0c\u4ece\u901a\u4fe1\u7f51\u7edc\u4f18\u5316\u5230\u5de5\u4e1a\u63a7\u5236\u7b49\u3002<\/li>\n\n\n\n
    • \u3000\u3000\u786c\u4ef6\u548c\u8f6f\u4ef6\u6c34\u5e73\u63d0\u5347\uff1a\u56fd\u9645\u9f99\u5934\u4f01\u4e1a\u7684FPGA\u5df2\u8fdb\u51657nm\u5236\u7a0b\uff0c\u5e76\u91c7\u7528\u4e86\u66f4\u524d\u6cbf\u7684\u5b58\u50a8\u4e0e\u4e92\u8fde\u6280\u672f\u3002\u800c\u56fd\u4ea7FPGA\u4ecd\u5904\u4e8e28nm\u541110nm\u7814\u53d1\u7684\u8fc7\u7a0b\u4e2d\u3002\u6d77\u5916FPGA\u5382\u5546\u5728\u8f6f\u4ef6\u6c34\u5e73\u4e0a\u4e5f\u6709\u6240\u63d0\u5347\u3002<\/li>\n<\/ul>\n\n\n\n

      \u3000\u3000FPGA\u7684\u6700\u65b0\u6280\u672f\u8fdb\u5c55\u4e3b\u8981\u96c6\u4e2d\u5728\u795e\u7ecf\u7f51\u7edc\u52a0\u901f\u3001\u5d4c\u5165\u5f0f\u7cfb\u7edf\u6280\u672f\u3001\u6027\u80fd\u548c\u53ef\u9760\u6027\u7684\u63d0\u5347\u3001\u4ee5\u53ca\u5728\u901a\u4fe1\u548c\u5927\u6570\u636e\u5904\u7406\u65b9\u9762\u7684\u5e94\u7528\u3002\u672a\u6765\u53d1\u5c55\u8d8b\u52bf\u5c06\u805a\u7126\u4e8e\u8fdb\u4e00\u6b65\u63d0\u9ad8\u6027\u80fd\u3001\u53ef\u9760\u6027\u4ee5\u53ca\u5728\u66f4\u591a\u9886\u57df\u7684\u5e94\u7528\u62d3\u5c55\uff0c\u540c\u65f6\u5728\u786c\u4ef6\u548c\u8f6f\u4ef6\u5c42\u9762\u6301\u7eed\u521b\u65b0\u4ee5\u4fdd\u6301\u7ade\u4e89\u529b\u3002<\/p>\n\n\n\n

      \u3000\u3000\u4e94\u3001 \u5728FPGA\u8bbe\u8ba1\u4e2d\uff0c\u5e38\u89c1\u7684\u7f16\u7a0b\u8bed\u8a00\u548c\u5de5\u5177\u6709\u54ea\u4e9b?<\/h2>\n\n\n\n

      \u3000\u3000\u5728FPGA\u8bbe\u8ba1\u4e2d\uff0c\u5e38\u89c1\u7684\u7f16\u7a0b\u8bed\u8a00\u4e3b\u8981\u5305\u62ecVerilog HDL\u3001VHDL\u548cSystemVerilog\u3002\u8fd9\u4e9b\u8bed\u8a00\u88ab\u5e7f\u6cdb\u5e94\u7528\u4e8eFPGA\u7684\u8bbe\u8ba1\u548c\u5f00\u53d1\u4e2d\uff0c\u5176\u4e2dVerilog HDL\u548cVHDL\u662f\u6700\u57fa\u672c\u7684\u786c\u4ef6\u63cf\u8ff0\u8bed\u8a00(HDL)\uff0c\u800cSystemVerilog\u5219\u63d0\u4f9b\u4e86\u4e00\u79cd\u66f4\u9ad8\u7ea7\u522b\u7684\u62bd\u8c61\uff0c\u4f7f\u5f97\u8bbe\u8ba1\u8005\u53ef\u4ee5\u66f4\u52a0\u65b9\u4fbf\u5730\u8fdb\u884c\u7cfb\u7edf\u7ea7\u7684\u8bbe\u8ba1\u548c\u9a8c\u8bc1\u3002<\/p>\n\n\n\n

      \u3000\u3000\u81f3\u4e8e\u5de5\u5177\u65b9\u9762\uff0cAltera\u516c\u53f8\u63d0\u4f9b\u4e86Quartus II\u4f5c\u4e3a\u5176\u96c6\u6210\u5f00\u53d1\u73af\u5883(IDE)\uff0c\u652f\u6301\u4ece\u8bbe\u8ba1\u8f93\u5165\u5230\u786c\u4ef6\u914d\u7f6e\u7684\u5b8c\u6574\u6d41\u7a0b\uff0c\u9002\u7528\u4e8e\u6570\u5b57\u4fe1\u53f7\u5904\u7406\u7b49\u5e94\u7528\u3002Xilinx\u516c\u53f8\u5219\u63d0\u4f9b\u4e86Vivado Design Suite\u548cVitis\u7edf\u4e00\u8f6f\u4ef6\u5e73\u53f0\uff0c\u5176\u4e2dVivado\u662f\u4e00\u4e2a\u7efc\u5408\u5de5\u5177\uff0c\u7528\u4e8eFPGA\u5b9e\u73b0\uff0c\u800cVitis HLS\u5de5\u5177\u5141\u8bb8\u7528\u6237\u901a\u8fc7\u5c06C\/C++\u51fd\u6570\u7efc\u5408\u81f3RTL\u4e2d\u6765\u521b\u5efa\u590d\u6742\u7684FPGA\u7b97\u6cd5\u3002\u6b64\u5916\uff0cIntel\u4e5f\u4e3a\u5176Altera FPGAs\u3001CPLDs\u548cSoC FPGAs\u63d0\u4f9b\u4e86\u4e00\u6574\u5957\u5f00\u53d1\u5de5\u5177\uff0c\u8986\u76d6\u4e86\u8bbe\u8ba1\u7684\u6bcf\u4e00\u4e2a\u9636\u6bb5\u3002<\/p>\n\n\n\n

      \u3000\u3000FPGA\u8bbe\u8ba1\u4e2d\u5e38\u7528\u7684\u7f16\u7a0b\u8bed\u8a00\u5305\u62ecVerilog HDL\u3001VHDL\u548cSystemVerilog\uff0c\u800c\u5e38\u7528\u7684\u5f00\u53d1\u5de5\u5177\u5219\u6709Altera\u7684Quartus II\u3001Xilinx\u7684Vivado Design Suite\u548cVitis\u7edf\u4e00\u8f6f\u4ef6\u5e73\u53f0\uff0c\u4ee5\u53caIntel\u63d0\u4f9b\u7684\u9488\u5bf9Altera FPGA\u7684\u5f00\u53d1\u5de5\u5177\u3002<\/p>\n","protected":false},"excerpt":{"rendered":"

      FPGA(Field-Programmable Gate Array)\uff0c\u5373\u73b0\u573a\u53ef\u7f16\u7a0b\u95e8\u9635\u5217\uff0c\u662f\u4e00\u79cd\u7535\u5b50\u8bbe\u5907\uff0c\u7528\u4e8e\u6267\u884c\u4efb\u4f55\u6570\u5b57\u903b\u8f91\u529f\u80fd\u6216\u6570\u5b57\u7535\u8def\u7684\u786c\u4ef6\u5b9e\u73b0\u3002<\/p>\n","protected":false},"author":1,"featured_media":90411,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"site-sidebar-layout":"default","site-content-layout":"default","ast-global-header-display":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","footnotes":""},"categories":[36],"tags":[305],"class_list":["post-91570","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","tag-dzjs"],"_links":{"self":[{"href":"https:\/\/www.techphant.cn\/wp-json\/wp\/v2\/posts\/91570","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.techphant.cn\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.techphant.cn\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.techphant.cn\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.techphant.cn\/wp-json\/wp\/v2\/comments?post=91570"}],"version-history":[{"count":0,"href":"https:\/\/www.techphant.cn\/wp-json\/wp\/v2\/posts\/91570\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.techphant.cn\/wp-json\/wp\/v2\/media\/90411"}],"wp:attachment":[{"href":"https:\/\/www.techphant.cn\/wp-json\/wp\/v2\/media?parent=91570"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.techphant.cn\/wp-json\/wp\/v2\/categories?post=91570"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.techphant.cn\/wp-json\/wp\/v2\/tags?post=91570"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}